University Park, Pa. --- Researchers from Penn State, the University of South Florida and the University of Texas at El Paso have developed and demonstrated a new method for reducing computer circuits' energy requirements -- by more than one-half in some applications-- without cutting down on overall operating speed.
The new approach holds promise for laptop and other personal computing device users worried about their batteries running down, manufacturers who want to make more complex circuits that won't melt in full operation, and wireless communication equipment developers that need dedicated circuits with lower power demands.
The method was described in January at the 12th International Conference on VLSI Design in a paper, "Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages." The authors are: Dr. Vamsi Krishna, University of South Florida; Dr. N. Ranganathan, The University of Texas at El Paso; and Dr. Vijaykrishnan Narayanan, assistant professor of computer science and engineering, Penn State.
Narayanan says their approach is based on combining the use of multiple voltages with a new concept, dynamic frequency clocking (DFC), which schedules energy resources on a flexible basis, according to the operations active within a circuit in a particular cycle. Energy is conserved by grouping operations in the most energy efficient patterns based on their critical path delay or the time it takes to complete the operation.
For example, Narayanan says, consider a circuit that includes three adders and a multiplier. Adders have a smaller critical path delay than multipliers. Grouping one of the fast adders with the slower multiplier allows the researchers to slow the adder down to the speed of the multiplier without slowing the overall process. To slow the adder down, the researchers supply it with a lower frequency and voltage which conserves energy. Higher voltages make signals propagate down wires faster but require more energy.
The researchers have, so far, performed simulations of their approach for some benchmark circuits particularly useful for signal and image processing computer architectures. They found that, with a suitable choice of voltage levels, their approach produces an average energy saving of 53.5 percent versus the standard, static, clocking scheme and single supply voltages.
The operation units used in the test case were three adders/subtractors and three multipliers. The voltage for the adders/subtractors could be 5.0V, 3.3V or 2.4V. The voltages for the multipliers could be either 5.0V or 3.3V. However, the authors note in their paper that their algorithm can be applied to any other combination of resource and time constraints.
In their paper, the authors note, "DFC is useful for signal and image processing applications where the complexity of operations varies. Certain procedures in such applications require only logic functions, while others require only additions and certain others multiplication or division."
The authors conclude," The results show good potential in energy minimization and can be used for a wide range of portable applications." Currently the research team is investigating using multi-cycling and chaining in conjunction with their approach for further performance improvements.
The above post is reprinted from materials provided by Penn State. Note: Materials may be edited for content and length.
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