University Park, Pa. - Researchers at Penn State's Microsystems Design Laboratory have developed a new energy estimation tool, called SimplePower, that not only evaluates a system-on-a chips' power consumption faster than other available techniques but also points out the power hungry "hotspots" in both hardware and software so that designers can fix them.
Dr. Vijaykrishnan Narayanan, assistant professor of computer science and engineering and one of SimplePower's developers, says, "Architectural level power estimation tools are becoming increasingly important with the growing complexity of current systems-on-a-chip designs to provide fast estimates of the energy consumption early in the design cycle. By the time the design of today's large and complex processors have been set in silicon, it may be too late or too expensive to go back and deal with excess power consumption problems."
"Software is becoming an important aspect of emerging embedded systems and the study of the integrated impact of software and hardware optimizations needs to be supported with new tools. SimplePower meets that need," he adds.
SimplePower was unveiled at the International Symposium on Computer Architecture (ISCA) this summer in Vancouver, British Columbia, Canada. The development team includes Dr. Mary Jane Irwin, professor of computer science and engineering, Narayanan, Dr. Mahmut Kandemir, assistant professor of computer science and engineering, and graduate students Wu Ye and Hyun Suk Kim. The developers are planning to make the prototype package available free of charge. More information is available at http://www.cse.psu.edu/~mdl.
Most architectural level power estimation techniques are based on actual measurements of individual existing chips and produce specific models from those measurements. SimplePower uses a "generic" chip, the instruction set of Simplescalar which is a suite of publicly available tools to simulate modern microprocessors. In addition, SimplePower is based on input transitions rather than input statistics. This method, first proposed by Irwin and colleagues in 1996, provides an energy model for each functional unit of the chip in a table containing the power consumed for each input transition. Closely related input transitions and energy patterns can be collapsed into clusters in order to reduce the size of the table.
SimplePower comes within 10 to 15 percent accuracy of circuit-level estimation techniques but produces results many times faster, for example, in a tenth of a nanosecond versus 9 minutes, says Narayanan.
In tests designed to illustrate SimplePower's optimization capabilities, the developers used the simulation tool to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a power-conscious post compilation optimization. They found that these three optimizations reduce the energy by 18-36 percent in the datapath, 62 percent in the memory system and 12 percent in the instruction cache data bus, respectively.
The researchers add, "In contrast to other methods, SimplePower is useful in optimizing the energy of the system as a whole and can capture the memory energy savings against that of the datapath. This capability is important when applying certain high-level transforms such as loop tiling that increase datapath energy."
SimplePower was detailed in a paper presented at the ISCA, Integrated Hardware-Software Optimizations Using SimplePower and two papers presented at the Design Automation Conference: The Design and Use of SimplePower: A Cycle-Accurate Energy Estimation Tool and Influence of Compiler Optimizations on System Power.
The above post is reprinted from materials provided by Penn State. Note: Materials may be edited for content and length.
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