Apr. 12, 2012 A pioneering error correction technique developed at the A*STAR Data Storage Institute holds promise for the development of next-generation computers.
Over the past decade, tablet computers and smartphones have taken the world by storm, in no small part due to the way in which they can be switched on almost instantly. The race has been on to develop computers that can similarly be up and running in a matter of moments. Such advances are currently hindered due to the fact that computers need to boot up, as silicon memory chips cannot hold information if the power is turned off. In order to retain information even if the power is turned off, the memory needs to be non-volatile, as is the type of memory commonly found in memory sticks. However, existing memory technologies are expensive, difficult to scale up and often cannot keep up with the demands of current desktop computers. A key contender for future non-volatile memories is the so-called spin-torque transfer magnetic random access memory (STT-MRAM).
For this reason, Cai and colleagues developed a new design of the memory sensing and detection architecture that is based on soft decision decoding. The soft decision decoding goes beyond the strict limitation of 0s and 1s of the bits and also considers the probability of each detected bit being a '0' or '1'. The use of such additional information leads to significantly fewer decoding errors than the hard decision decoding that does not take such probabilities into account.
Improving performance across the board
An important component of the new design is the soft-output channel detector, which measures the probabilities of the bits read out being set as '0' and '1', and feeds this information into the soft decision decoding process of the particular STT-MRAM error correction code utilized here -- the so-called low-density parity-check (LDPC) codes.
The improved design also includes a new quantization scheme for STT-MRAM. This is the process that converts the analogue signal into the digital signal. To ensure a high-quality conversion, the analogue information is best encoded into a large number of quantization bits, which greatly increases computational efforts. However, the enhanced error correction procedure means that fewer quantization bits can be used. This not only simplifies the management of such devices but also maximizes the number of information bits that can be stored in a STT-MRAM cell.
Remarkably, Cai and her colleagues have successfully shown that the new scheme achieves a 20% increase in the tolerance towards variations in electrical resistance of the devices. Such relaxed demands greatly ease the manufacturing process of the devices and also will be important when it comes to further reducing STT-MRAM device sizes, as Alexopoulos comments: "DSI's design of LDPC coding with soft decision decoding for STT-MRAM has a better error correction capability, paving the way for the industry to reduce the cell feature size of future STT-MRAM devices."
The new error correction approach developed by Cai may well keep STT-MRAM in the running when it comes to replacing flash drives in computers, and lengthy computer boot-up times could soon be a thing of the past. One of the next challenges for the non-volatile memory coding team will be to focus on further scaling of STT-MRAM. "We will further investigate how ECCs with soft decoding can help to improve the various performance of STT-MRAM, and eventually contribute to the scaling of STT-MRAM," says Cai. "We will also design different ECCs for STT-MRAM with different applications."
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The above story is reprinted from materials provided by The Agency for Science, Technology and Research (A*STAR).
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