Godiva's Speedy Ride: USC PIM Chip On Track To Beat Itanium

The Godiva chip uses a DDR-DRAM interface and "the server uses it as if it were standard memory," said Hall. Hall and Draper will discuss their work at the SC2004 High Performance Computing Conference Nov. 8-10 in Pittsburgh PA.

ISI has completed StreamAdd benchmarking, which measures memory bandwidth, on a single Godiva chip running as part of the Long's Peak system.

The result: the measured throughput of the Godiva chip and the original-equipment Itanium chip is roughly the same. "But our chip uses only one hundredth the electrical power of the Itanium," noted Draper.

Like other PIM chips, Godiva is an effort to minimize the communication bottleneck that takes place when processing chips have to go back and forth to separate memory chips to get data for computations, and then store the results. "The theory," said Draper, "is that a PIM chip can keep results and data in its own memory, resulting in dramatic gains in speed. We now see these results in actual benchmarking."

The system was benchmarked with only a single Godiva chip in place. But Hall notes that the chip was designed to be used in 8-chip configurations. "The bottom line is we will deliver 8 times the computing power using less than one tenth of the electricity."

The mismatch goes farther. Because the Godiva effort was a proof-of-concept academic research project, the Godiva team used a relatively slow clock rate — one-sixth the rate of the Itanium.

"A commercial implementation could operate at a state-of-the-art clock rate," said Hall, who added that benchmarking was continuing in other standard measures of performance.

"But we believe that for certain uses that demand high memory bandwidth, such as multimedia, complex scientific modeling and database access, and knowledge discovery, the existing Godiva chip will deliver at least the order-of-magnitude performance improvement that our initial design was aimed at achieving, and likely significantly more."

The 56-million transistor Godiva chip improves on an earlier PIM chip created in a previous ISI project called DIVA. Godiva added address translation and eight single-precision floating point units, and contains a memory interface compatible with DDR SDRAM memory buses.

One of the largest chips ever realized in academia, Godiva was fabricated at Taiwan Semiconductor Manufacturing Corporation (TSMC) through ISI's MOSIS chip brokerage

Besides Hall and Draper, the Godiva team includes ISI researchers Jacqueline Chame (Compiler and Application Benchmarking), Tim Barrett (System Integration), Jeff Sondeen (VLSI), Dale Chase (System Integration), Spundun Bhatt (Compiler and System Software), and many ISI graduate students.

Defense agencies including DARPA and the Air Force Research Laboratory (AFRL) funded the project.