The next generation of laptops, desk computers, cell phones and other semiconductor devices may get faster and more cost-effective with research from Clemson University.
“We’ve developed a new process and equipment that will lead to a significant reduction in heat generated by silicon chips or microprocessors while speeding up the rate at which information is sent,” says Rajendra Singh, D. Houser Banks Professor and director for the Center for Silicon Nanoelectronics at Clemson University.
The heart of many high-tech devices is the microprocessor that performs the logic functions. These devices produce heat depending on the speed at which the microprocessor operates. Higher speed microprocessors generate more heat than lower speed ones. Presently, dual-core or quad-core microprocessors are packaged as a single product in laptops so that heat is reduced without compromising overall speed of the computing system. The problem, according to Singh, is that writing software for these multicore processors, along with making them profitable, remains a challenge.
“Our new process and equipment improve the performance of the materials produced, resulting in less power lost through leakage. Based on our work, microprocessors can operate faster and cooler. In the future it will be possible to use a smaller number of microprocessors in a single chip since we’ve increased the speed of the individual microprocessors. At the same time, we’ve reduced power loss six-fold to a level never seen before. Heat loss and, therefore, lost power has been a major obstacle in the past,” said Singh.
The researchers say the patented technique has the potential to improve the performance and lower the cost of next-generation computer chips and a number of semiconductor devices, which include green energy conversion devices such as solar cells.
“The potential of this new process and equipment is the low cost of manufacturing, along with better performance, reliability and yield,” Singh said. “The semiconductor industry is currently debating whether to change from smaller (300 mm wafer) manufacturing tools to larger ones that provide more chips (450 mm). Cost is the barrier to change right now. This invention potentially will enable a reduction of many processing steps and will result in a reduction in overall costs.”
Participants in the research included Aarthi Venkateshan, Kelvin F. Poole, James Harriss, Herman Senter, Robert Teague of Clemson and J. Narayan of North Carolina State University at Raleigh. Results were published in Electronics Letters, Oct. 11, 2007, Volume: 43, Issue: 21, pages: 1130-1131. The work reported here is covered by a broad-base patent of Singh and Poole issued to Clemson University in 2003.
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