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Team reports scalable fabrication of self-aligned graphene transistors, circuits

Date:
June 20, 2011
Source:
University of California - Los Angeles
Summary:
Researchers previously reported a self-aligned technique for making graphene transistors with unparalleled speed, but scalability was a question. The team now uses a dielectrophoresis assembly approach to precisely place nanowire gate arrays on large area chemical vapor deposition growth graphene to enable the rational fabrication of high speed transistor arrays. They also did this on a glass substrate, minimizing the parasitic delay and enabling graphene transistors with extrinsic cut-off frequencies exceeding 50 GHz.

Self-aligned graphene transistor array.
Credit: Image courtesy of UCLA

Graphene, a one-atom-thick layer of graphitic carbon, has the potential to make consumer electronic devices faster and smaller. But its unique properties, and the shrinking scale of electronics, also make graphene difficult to fabricate and to produce on a large scale.

In September 2010, a UCLA research team reported that they had overcome some of these difficulties and were able to fabricate graphene transistors with unparalleled speed. These transistors used a nanowire as the self-aligned gate -- the element that switches the transistor between various states. But the scalability of this approach remained an open question.

Now the researchers, using equipment from the Nanoelectronics Research Facility and the Center for High Frequency Electronics at UCLA, report that they have developed a scalable approach to fabricating these high-speed graphene transistors.

The team used a dielectrophoresis assembly approach to precisely place nanowire gate arrays on large-area chemical vapor deposition-growth graphene -- as opposed to mechanically peeled graphene flakes -- to enable the rational fabrication of high-speed transistor arrays. They were able to do this on a glass substrate, minimizing parasitic delay and enabling graphene transistors with extrinsic cut-off frequencies exceeding 50 GHz. Typical high-speed graphene transistors are fabricated on silicon or semi-insulating silicon carbide substrates that tend to bleed off electric charge, leading to extrinsic cut-off frequencies of around 10 GHz or less.

Taking an additional step, the UCLA team was able to use these graphene transistors to construct radio-frequency circuits functioning up to 10 GHz, a substantial improvement from previous reports of 20 MHz.

The research opens a rational pathway to scalable fabrication of high-speed, self-aligned graphene transistors and functional circuits and it demonstrates for the first time a graphene transistor with a practical (extrinsic) cutoff frequency beyond 50 GHz.

This represents a significant advance toward graphene-based, radio-frequency circuits that could be used in a variety of devices, including radios, computers and mobile phones. The technology might also be used in wireless communication, imaging and radar technologies.

The UCLA research team included Xiangfeng Duan, professor of chemistry and biochemistry; Yu Huang, assistant professor of materials science and engineering at the Henry Samueli School of Engineering and Applied Science; Lei Liao; Jingwei Bai; Rui Cheng; Hailong Zhou; Lixin Liu; and Yuan Liu.

Duan and Huang are also researchers at the California NanoSystems Institute at UCLA.

The work was funded by grants from National Science Foundation and the National Institutes of Health.

The research was recently published in the peer-reviewed journal Nano Letters.


Story Source:

The above story is based on materials provided by University of California - Los Angeles. The original article was written by Mike Rodewald. Note: Materials may be edited for content and length.


Journal Reference:

  1. Lei Liao, Jingwei Bai, Rui Cheng, Hailong Zhou, Lixin Liu, Yuan Liu, Yu Huang, Xiangfeng Duan. Scalable fabrication of self-aligned graphene transistors and circuits on glass. Nano Letters, 2011; 110607115253088 DOI: 10.1021/nl201922c

Cite This Page:

University of California - Los Angeles. "Team reports scalable fabrication of self-aligned graphene transistors, circuits." ScienceDaily. ScienceDaily, 20 June 2011. <www.sciencedaily.com/releases/2011/06/110617110710.htm>.
University of California - Los Angeles. (2011, June 20). Team reports scalable fabrication of self-aligned graphene transistors, circuits. ScienceDaily. Retrieved July 22, 2014 from www.sciencedaily.com/releases/2011/06/110617110710.htm
University of California - Los Angeles. "Team reports scalable fabrication of self-aligned graphene transistors, circuits." ScienceDaily. www.sciencedaily.com/releases/2011/06/110617110710.htm (accessed July 22, 2014).

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