Laptop computers, Palm Pilots and cellular phones all rely on the fixed amount of energy in their batteries to function, but that precious power is not used as efficiently as it could be. Now, a team of electrical and computer engineers at Northwestern University is working to develop low-power computing systems that could breathe longer life into battery-powered, portable devices.
The team, led by Prith Banerjee, Walter P. Murphy Professor of Electrical and Computer Engineering, is not focusing on improving batteries but instead is looking at the complex architecture of the computer and its utilization of power to complete tasks. Currently, much of a battery’s power is wasted.
With a three-year, $2 million grant from the Defense Advanced Projects Research Agency (DARPA), Banerjee and his colleagues plan to develop novel architectural and compiler concepts that can reduce total energy consumption in specific military applications by a factor of 100 times over conventional, non-power-aware computer architectures.
Power-aware computing is needed to improve the performance of military devices, such as satellites and missiles. Satellite missions, for example, could be lengthened or made more complex if their systems managed power effectively and efficiently in response to changing environmental and mission conditions. Entirely new missions could be possible with improved technology.
While the researchers are focusing their efforts on military applications, the new technology also will benefit civilian applications. To help ensure technology transfer to the commercial sector, the Northwestern team is collaborating with Motorola Corporation and Cadence Design Systems throughout the project.
"In developing a low-power system, we essentially want to shut off different components of the computer when they are not needed," said Banerjee, an expert in compilers and computer-aided design (CAD). "Success requires an integrated approach. We need to develop both code that drives the computer in a smart way and architecture that can execute the code’s commands."
The challenge lies in creating a totally integrated low-power computing system, something that has yet to be done. Others in industry have contributed singular techniques that reduce the use of power, but no one has approached the problem as comprehensively as the Northwestern team.
The integrated system will rely on three key parts: power-aware CAD tools, a power-aware compiler and power-aware hardware or architecture.
Focusing on memory and processor hardware, the researchers will use CAD tools to design new components and chips that use less power. When designing the compiler, which translates the software into machine code, they will need to integrate it with the new hardware architecture. The CAD tools also will be used to test the design of the new system and determine if the amount of power it consumes is acceptable.
At the end of the three-year project, the Northwestern team will demonstrate the usefulness of the new power-aware system on real military applications.
"We can make computers more intelligent," said Banerjee. "By using battery resources in a smart way, the new devices will have the power to do more things, whether it be a more complicated satellite mission or a laptop computer that can perform more functions. An added bonus is that your laptop may require battery recharging only once a week, instead of every six hours."
Other members of the team include professors Majid Sarrafzadeh, Alok Choudhary, Andreas Moshovos and Horace Yuen, all of Northwestern’s department of electrical and computer engineering. Further information on the project can be found at http://www.ece.northwestern.edu/cpdc/PACT/.
The above post is reprinted from materials provided by Northwestern University. Note: Content may be edited for style and length.
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